Freescale Semiconductor /MK20D10 /SDHC /PROCTL

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Interpret as PROCTL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)LCTL 0 (00)DTW0 (0)D3CD 0 (00)EMODE 0 (0)CDTL 0 (0)CDSS 0 (00)DMAS 0 (0)SABGREQ 0 (0)CREQ 0 (0)RWCTL 0 (0)IABG 0 (0)WECINT 0 (0)WECINS 0 (0)WECRM

WECRM=0, EMODE=00, D3CD=0, SABGREQ=0, CDSS=0, IABG=0, RWCTL=0, WECINS=0, DMAS=00, WECINT=0, CREQ=0, CDTL=0, DTW=00, LCTL=0

Description

Protocol Control register

Fields

LCTL

LED Control

0 (0): LED off.

1 (1): LED on.

DTW

Data Transfer Width

0 (00): 1-bit mode

1 (01): 4-bit mode

2 (10): 8-bit mode

D3CD

DAT3 As Card Detection Pin

0 (0): DAT3 does not monitor card Insertion.

1 (1): DAT3 as card detection pin.

EMODE

Endian Mode

0 (00): Big endian mode

1 (01): Half word big endian mode

2 (10): Little endian mode

CDTL

Card Detect Test Level

0 (0): Card detect test level is 0, no card inserted.

1 (1): Card detect test level is 1, card inserted.

CDSS

Card Detect Signal Selection

0 (0): Card detection level is selected for normal purpose.

1 (1): Card detection test level is selected for test purpose.

DMAS

DMA Select

0 (00): No DMA or simple DMA is selected.

1 (01): ADMA1 is selected.

2 (10): ADMA2 is selected.

SABGREQ

Stop At Block Gap Request

0 (0): Transfer

1 (1): Stop

CREQ

Continue Request

0 (0): No effect.

1 (1): Restart

RWCTL

Read Wait Control

0 (0): Disable read wait control, and stop SD clock at block gap when SABGREQ is set.

1 (1): Enable read wait control, and assert read wait without stopping SD clock at block gap when SABGREQ bit is set.

IABG

Interrupt At Block Gap

0 (0): Disabled

1 (1): Enabled

WECINT

Wakeup Event Enable On Card Interrupt

0 (0): Disabled

1 (1): Enabled

WECINS

Wakeup Event Enable On SD Card Insertion

0 (0): Disabled

1 (1): Enabled

WECRM

Wakeup Event Enable On SD Card Removal

0 (0): Disabled

1 (1): Enabled

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